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HS-6617RH
TM
Data Sheet
August 2000
File Number
3033.4
Radiation Hardened 2K x 8 CMOS PROM
The Intersil HS-6617RH is a radiation hardened 16K CMOS PROM, organized in a 2K word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, and is designed to be functionally equivalent to the HM-6617. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. On chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structure, such as the HS-80C85RH or HS-80C86RH. The output enable control (G) simplifies microprocessor system interfacing by allowing output data bus control, in addition to, the chip enable control. Synchronous operation of the HS-6617RH is ideal for high speed pipe-lined architecture systems and also in synchronous logic replacement functions. Applications for the HS-6617RH CMOS PROM include low power microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchronous logic replacement. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95708. A "hot-link" is provided on our homepage for downloading. http://www.intersil.com/spacedefense/space.htm
Features
* Electrically Screened to SMD # 5962-95708 * QML Qualified per MIL-PRF-38535 Requirements * Total Dose . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max) * Latch-Up Free. . . . . . . . . . . . . . . . . . . . >1 x 1012 rad(Si)/s * Field Programmable * Functionally Equivalent to HM-6617 * Pin Compatible with Intel 2716 * Low Standby Power . . . . . . . . . . . . . . . . . . . 1.1mW (Max) * Low Operating Power . . . . . . . . . . . . 137.5mW/MHz (Max) * Fast Access Time . . . . . . . . . . . . . . . . . . . . . . 100ns (Max) * TTL Compatible Inputs/Outputs * Synchronous Operation * On Chip Address Latches * Three-State Outputs * Nicrome Fuse Links * Easy Microprocessor Interfacing * Military Temperature Range . . . . . . . . . . . -55oC to 125oC
Ordering Information
ORDERING NUMBER 5962R9570801QJC 5962R9570801QXC 5962R9570801VJC 5962R9570801VXC HS1-6617RH/PROTO HS9-6617RH/PROTO INTERNAL MKT. NUMBER HS1-6617RH-8 HS9-6617RH-Q HS1-6617RH-Q HS9-6617RH-Q HS1-6617RH/PROTO HS9-6617RH/PROTO TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
HS-6617RH Pinouts
24 LEAD CERAMIC DUAL-IN-LINE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW
A7 A6 A5 A4 A3 A2 A1 A0 Q0 1 2 3 4 5 6 7 8 9 24 VDD 23 A8 22 A9 21 P 20 G 19 A10 18 E 17 Q7 16 Q6 15 Q5 14 Q4 13 Q3
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW
A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD A8 A9 P G A10 E Q7 Q6 Q5 Q4 Q3
Q1 10 Q2 11 GND 12
PIN A Q E G P Address Input Data Output Chip Enable Output Enable
DESCRIPTION
Program Enable (P Hardwired to VDD, except during programming)
Functional Diagram
A10 A9 A8 A7 A6 A5 A4 MSB 7 LATCHED ADDRESS REGISTER LSB E P E 8 16 16 16 16 16 16 16 16 8 Q0 - Q7 7 A A GATED ROW DECODER 128 1 OF 8 128 x 128 MATRIX
GATE COLUMN DECODER PROGRAMMING, & DATA
E E A G
OUTPUT CONTROL 4 A 4
E
LATCHED ADDRESS REGISTER ALL LINES POSITIVE LOGIC: ACTIVE HIGH THREE STATE BUFFERS: A HIGH OUTPUT ACTIVE
ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G P = HARDWIRED TO VDD EXCEPT DURING PROGRAMMING
MSB A3 A2 A1 A0
LSB
TRUTH TABLE E 0 0 1 G 0 1 X Enabled Output Disabled Disabled MODE
2
HS-6617RH Timing Waveform
TAVQV 3.0V 1.5V 1.5V VALID ADDRESS ADDRESSES TELEL TAVEL TELAX TELEH 3.0V 1.5V E TEHEL G 1.5V TGLQX TELQX VALID DATA TS TELQV TGLQV 1.5V 0V TGHQZ TEHQZ 3.0V 1.5V 1.5V 1.5V 0V VALID ADDRESSES 0V
DATA OUTPUT Q0 - Q7
FIGURE 1. READ CYCLE
Burn-In Circuits
HS-6617RH 24 LEAD SBDIP AND FLATPACK
C1 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Y Q1 Q2 GND VDD A8 A9 P G A10 E Q7 Q6 Q5 Q4 Q3 Y Y A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND VDD A8 A9 P G A10 E Q7 Q6 Q5 Q4 Q3 Y
HS-6617RH 24 LEAD SBDIP AND FLATPACK
C1
VDD VDD VDD VDD VDD VDD VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD VDD VDD VDD VDD VDD VDD
F10 F9 F8 F7 F6 F5 F4 F3
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD F11 F12 VDD F1 F13 F0
STATIC CONFIGURATION NOTES: 1. VDD = 6.0V 0.5V 2. C1 = 0.01F (Min) 3. All Resistors = 47k 5% 4. Y = 2.7V 10% NOTES:
DYNAMIC CONFIGURATION 5. VDD = 6.0V 0.5V 6. VIH = 4.5V 10% 7. VIL = 0.8V (Max) 8. C1 = 0.01F (Min) 9. All Resistors = 47k 5% 10. F0 = 100KHz 10%, 40 - 60% duty cycle 11. F1 = F0/2 . . . F13 = F12/2 12. Y = 2.7V 10%
3
HS-6617RH Irradiation Circuit
HS-6617RH 24 LEAD FLATPACK
VDD
1 2 3 4 5 6 7 8 LOAD LOAD LOAD 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13 LOAD LOAD LOAD LOAD LOAD 47K VSS 47K LOAD = NC NC NC TOGGLE (NOTE 15) VDD
NOTES: 13. Power Supply: VDD = 5.5V 14. All Registors = 47k 15. Pin 18 is toggled from VSS to VDD then back to VSS and held at VSS during irradiation.
4
HS-6617RH Die Characteristics
DIE DIMENSIONS: 164mils x 250mils x 19mils 1mils INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8kA 1kA Top Metallization: Type: Silicon-Aluminum Thickness: 13kA 2kA ASSEMBLY RELATED INFORMATION: Substrate Potential: VDD ADDITIONAL INFORMATION: Worst Case Current Density: 1 x 105 A/cm2
Metallization Mask Layout
HS-6617RH
(24)VDD (23) A8 (22) A9 (5) A3 (4) A4 (2) A6 (1) A7 (21) P (3)A5
(20) G A2 (6) (19) A10
A1 (7) A0 (8) GND (12) Q1 (10) Q2 (11) Q3 (13) Q4 (14) Q5 (15) Q6 (16) Q7 (17) Q0 (9)
(18) E
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 5

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